The advent of the integrated circuit has had a significant impact on various types of communication devices. The integrated circuit has been incorporated into both radio frequency applications and high speed communication network systems. While operation speeds of these communication devices have dramatically increased, the demand for yet faster communication devices continues to rise. Thus, the semiconductor manufacturing industry continually strives to increase the overall speed of the integrated circuit.
One way in which the semiconductor industry has increased the speed of the integrated circuit is to continue to shrink the size of the transistor. Over the last few years, the device size of the transistor has gone from 0.5 μm to 0.32 μm to 0.25 μm and now transistor device sizes are heading to the 0.10 μm range and below. With each decrease in size, however, the semiconductor industry has faced new challenges.
One of such challenges is that of reducing parasitic capacitance. As transistor geometries shrink, the time delay of signals propagating through the transistor are heavily influenced by the various parasitic capacitances inevitably associated with the structure, when fabricated according to the current state of the art. One of the principal remaining elements of transistor capacitance is the source-drain to substrate capacitance. This junction capacitance, as a function of area, is increasing as the technology advances. This is in part because one of the principal known failure mechanisms of a short channel transistor is controlled through the use of increased well doping. Increased well doping reduces the diode depletion layer thickness in the well, which increases unit capacitance.
Another challenge is reducing “cross-talk.” As is well known, cross-talk results when electrical noise, created by transistor devices, travels through the capacitive coupling of the substrate and negatively affects the performance of opposing devices. Though cross-talk has been a well-known phenomenon, up until recently it was of less concern. However, as a result of the use of multi-gigahertz operating frequencies in today's RF devices, the significance of cross-talk has increased dramatically. In addition, with the increase in packing density and decrease in device size, transistor devices are being manufactured on the same chip and closer and closer together, which increases the relative effect of the cross-talk problem. Thus, as a result of the increased packing density and the decreased device sizes, both taken in conjunction with the cross-talk problems, device performance and integration issues are becoming increasingly apparent.
Silicon-on-insulator (SOI) already provides a solution to these problems. However, this approach can require the use of a very high current implanter and a very high thermal budget. The use of the very high current implanter and very high thermal budget generally leads to increased manufacturing time, complexity, and most importantly, increased manufacturing cost. Additionally, the use of SOI may result in the transistor device having a floating back gate. Since the back gate of the transistor device is floating, the operational voltages may float up or down, possibly rendering the device either non-conducting or conducting at all times. Because of the four aforementioned drawbacks of SOI, the semiconductor manufacturing industry is generally unwilling to use the SOI structure on many conventional semiconductor devices.
Accordingly, what is needed in the art is a transistor device and a method of manufacture thereof, that does not experience the parasitic capacitance and “cross-talk” problems associated with the prior art transistors, and does not require the expense, time and effort to fabricate SOI substrates.